Design, simulation and hardware validation of a low-cost CLMS echo canceling system

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URI: https://hdl.handle.net/11556/1923
ISBN: 9781424445738
DOI: 10.1109/NEWCAS.2009.5290486
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2009
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This paper presents the design, simulation and performance of a low-cost echo canceler for its application to on-channel repeaters in single frequency DVB-T networks. In these devices an echo canceler is required in order to avoid the coupling echoes produced between transmission and reception antennas. The designed echo canceler is based on an adaptive FIR Alter where a correlation-based LMS algorithm (namely, CLMS) is used for updating the set of complex coefficients under a Minimum Squared Error (MSE) criteria. The implemented prototype includes an Analog Devices floating-point DSP and a Virtex II Pro FPGA core. Computer simulation results and the registered in-lab measurements of the prototype verify that our approach shows surprisingly satisfactory echo attenuation capabilities at a minimal computational cost.
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Hardware and Architecture , Control and Systems Engineering , Electrical and Electronic Engineering
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Prieto , P , Sanchez , M , Ser , J D & Mendicute , M 2009 , Design, simulation and hardware validation of a low-cost CLMS echo canceling system . in 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 . , 5290486 , 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 , 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 , Toulouse , France , 28/06/09 . https://doi.org/10.1109/NEWCAS.2009.5290486
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