RT Journal Article
T1 FPGA solution for matrix converter double sided space vector modulation algorithm
A1 Andreu, J.
A1 Bidarte, U.
A1 Astarloa, A.
A1 De Alegria, I. Martinez
A1 Ibanez, P.
AB Matrix Converters (MCs) present several advantages, but yet several barriers must be overcome, such as MC modulation and control technique complexity. This article proposes a multiplatform environment that allows the implementation of the Double Sided Space Vector Modulation (DS-SVM) algorithm in a last-generation Field Programmable Gate Array (FPGA) device. The traditional digital control architecture, based on a SP and some additional devices, is improved by means of a last generation FPGA where the main processor (PowerPC), internal memory, communication interfaces, I/O capabilities and a hardware core that executes the DS-SVM have been connected using on-chip buses. The methodology begins by defining the DS-SVM in a Matlab-Simulink environment. The PowerPC delivers 680 MIPS, but it is not a good candidate to execute the DS-SVM algorithm because it is not possible to achieve the modulation frequency that is necessary for an MC. A new configurable hardware circuit that implements the whole DS-SVM algorithm is proposed. This solution achieves modulation frequencies over 100 kHz. This hardware core is connected to one of the PowerPC buses and the processor can configure it or get feedback information at any time. As the processor is liberated from the very time-consuming DS-SVM computation, it can execute many higher level tasks.
SN 0020-7217
YR 2008
FD 2008-01
LK https://hdl.handle.net/11556/3646
UL https://hdl.handle.net/11556/3646
LA eng
NO Andreu , J , Bidarte , U , Astarloa , A , De Alegria , I M & Ibanez , P 2008 , ' FPGA solution for matrix converter double sided space vector modulation algorithm ' , International Journal of Electronics , vol. 95 , no. 11 , pp. 1181-1200 . https://doi.org/10.1080/00207210802387544
NO The present article has been financed by ‘‘Ministerio de Educación y Ciencia’’ and ‘‘FEDER’’ within the research project ENE 2007-67033-C03–02.
DS TECNALIA Publications
RD 28 jul 2024