%0 Generic
%A Kretzschmar, U.
%A Astarloa, A.
%A Lazaro, J.
%A Garay, M.
%A Del Ser, J.
%T Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA
%J 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012
%D 2012
%U https://hdl.handle.net/11556/1933
%X Triple Module Redundancy (TMR) is a popular technique for protecting critical FPGA designs. Although automatic tools for TMR generation mostly use triplication on flip-flop level, designers may opt for different approaches. This work analyses the impact of different granularities on TMR architectures based on a coarse-and a medium-grained TMR implementation of a shared Wishbone interconnection. The actual robustness of these different implementations is measured on a Xilinx Virtex-5 FPGA by using error injection into the configuration bitstream. A specialized test setup comprising two FPGAs boards is introduced so as to allow for the execution of the robustness testing. Based on the coarse-grained architecture, a fine categorization of errors in TMR architectures can be obtained.
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