RT Journal Article
T1 Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs
A1 Kretzschmar, Uli
A1 Gomez-Cornejo, Julen
A1 Astarloa, Armando
A1 Bidarte, Unai
A1 Del Ser, Javier
AB The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion.
YR 2016
FD 2016-07-01
LA eng
NO Kretzschmar , U , Gomez-Cornejo , J , Astarloa , A , Bidarte , U & Del Ser , J 2016 , ' Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs ' , unknown , vol. unknown , pp. 1-9 . https://doi.org/10.1016/j.ress.2015.12.018
NO Publisher Copyright: © 2016 Elsevier Ltd. All rights reserved.
DS TECNALIA Publications
RD 1 jul 2024