Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

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dc.contributor.authorKretzschmar, Uli
dc.contributor.authorGomez-Cornejo, Julen
dc.contributor.authorAstarloa, Armando
dc.contributor.authorBidarte, Unai
dc.contributor.authorDel Ser, Javier
dc.contributor.institutionIA
dc.date.issued2016-07-01
dc.descriptionPublisher Copyright: © 2016 Elsevier Ltd. All rights reserved.
dc.description.abstractThe expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion.en
dc.description.statusPeer reviewed
dc.format.extent9
dc.format.extent1657087
dc.identifier.citationKretzschmar , U , Gomez-Cornejo , J , Astarloa , A , Bidarte , U & Del Ser , J 2016 , ' Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs ' , unknown , vol. unknown , pp. 1-9 . https://doi.org/10.1016/j.ress.2015.12.018
dc.identifier.doi10.1016/j.ress.2015.12.018
dc.identifier.otherresearchoutputwizard: 11556/145
dc.identifier.urlhttp://www.scopus.com/inward/record.url?scp=84960344714&partnerID=8YFLogxK
dc.language.isoeng
dc.relation.ispartofunknown
dc.rightsinfo:eu-repo/semantics/restrictedAccess
dc.subject.keywordsReliability
dc.subject.keywordsTMR
dc.subject.keywordsFPGA
dc.subject.keywordsSynchronization
dc.subject.keywordsFault-recovery
dc.subject.keywordsProcessor
dc.subject.keywordsReliability
dc.subject.keywordsTMR
dc.subject.keywordsFPGA
dc.subject.keywordsSynchronization
dc.subject.keywordsFault-recovery
dc.subject.keywordsProcessor
dc.subject.keywordsSafety, Risk, Reliability and Quality
dc.subject.keywordsIndustrial and Manufacturing Engineering
dc.subject.keywordsFunding Info
dc.subject.keywordsMinisterio de Economia y Competitividad de España, TEC2014-53785-R_x000D_ Basque Government, IT394-10
dc.subject.keywordsMinisterio de Economia y Competitividad de España, TEC2014-53785-R_x000D_ Basque Government, IT394-10
dc.titleSynchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designsen
dc.typejournal article
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