Browsing by Keyword "Hardware core"
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Item Diseño de un convertidor matricial con control integrado(2010-04) Revenga-González, Julen; Andreu-Larrañaga, Jon; Ormaetxea-Gardoqui, Enekoitz; Bidarte-Peraita, Unai; Pedro, Ibáñez Ereño; SGThe matrix topology in AC/AC power converters presents several interesting advantages compared to other topologies, such as the decrease of the price, the size and the weight. However, despite these advantages, several technological barriers must be suppressed to find it interesting for an industrial production. Some of these causes are related to the complexity and the speed needed by those converters for the computational algorithm modulation; others are related directly to the complexity of the additional protection strategies required. This article presents a solution based on an FPGA (Field Programmable Gate Array) that helps to solve these problems and describes how to provide a cost-effective solution that will allow the industrial market of the Matrix Power Converters in the future.Item FPGA solution for matrix converter double sided space vector modulation algorithm(2008-01) Andreu, J.; Bidarte, U.; Astarloa, A.; De Alegria, I. Martinez; Ibanez, P.; SGMatrix Converters (MCs) present several advantages, but yet several barriers must be overcome, such as MC modulation and control technique complexity. This article proposes a multiplatform environment that allows the implementation of the Double Sided Space Vector Modulation (DS-SVM) algorithm in a last-generation Field Programmable Gate Array (FPGA) device. The traditional digital control architecture, based on a SP and some additional devices, is improved by means of a last generation FPGA where the main processor (PowerPC), internal memory, communication interfaces, I/O capabilities and a hardware core that executes the DS-SVM have been connected using on-chip buses. The methodology begins by defining the DS-SVM in a Matlab-Simulink environment. The PowerPC delivers 680 MIPS, but it is not a good candidate to execute the DS-SVM algorithm because it is not possible to achieve the modulation frequency that is necessary for an MC. A new configurable hardware circuit that implements the whole DS-SVM algorithm is proposed. This solution achieves modulation frequencies over 100 kHz. This hardware core is connected to one of the PowerPC buses and the processor can configure it or get feedback information at any time. As the processor is liberated from the very time-consuming DS-SVM computation, it can execute many higher level tasks.Item A matrix converter control embedded in a single system on chip based on a FPGA(2010) Ormaetxea, E.; Andreu, J.; Kortabarria, I.; Martínez De Alegría, I.; Robles, E.; RENOVABLES OFFSHOREThe matrix converter (MC) presents a promising topology that needs to overcome certain barriers (complexity of the modulation and control techniques, protection systems, etc.) in order to gain a foothold in the industry. This article deals with the implementation of the DS SVM vector modulation, commutation and protection of the MC through a series of hardware blocks (cores) integrally implemented in an FPGA. Likewise, given that all the processing capabilities have been integrated in a single chip, it can be said that an FPGA-based System on a Chip (SoC) has been designed.