Browsing by Keyword "FPGA"
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Item Efficient Neural Network Implementations on Parallel Embedded Platforms Applied to Real-Time Torque-Vectoring Optimization Using Predictions for Multi-Motor Electric Vehicles(2019-02) Dendaluce Jahnke, Martin; Cosco, Francesco; Novickis, Rihards; Pérez Rastelli, Joshué; Gomez-Garay, Vicente; Tecnalia Research & Innovation; CCAMThe combination of machine learning and heterogeneous embedded platforms enables new potential for developing sophisticated control concepts which are applicable to the field of vehicle dynamics and ADAS. This interdisciplinary work provides enabler solutions -ultimately implementing fast predictions using neural networks (NNs) on field programmable gate arrays (FPGAs) and graphical processing units (GPUs)- while applying them to a challenging application: Torque Vectoring on a multi-electric-motor vehicle for enhanced vehicle dynamics. The foundation motivating this work is provided by discussing multiple domains of the technological context as well as the constraints related to the automotive field, which contrast with the attractiveness of exploiting the capabilities of new embedded platforms to apply advanced control algorithms for complex control problems. In this particular case we target enhanced vehicle dynamics on a multi-motor electric vehicle benefiting from the greater degrees of freedom and controllability offered by such powertrains. Considering the constraints of the application and the implications of the selected multivariable optimization challenge, we propose a NN to provide batch predictions for real-time optimization. This leads to the major contribution of this work: efficient NN implementations on two intrinsically parallel embedded platforms, a GPU and a FPGA, following an analysis of theoretical and practical implications of their different operating paradigms, in order to efficiently harness their computing potential while gaining insight into their peculiarities. The achieved results exceed the expectations and additionally provide a representative illustration of the strengths and weaknesses of each kind of platform. Consequently, having shown the applicability of the proposed solutions, this work contributes valuable enablers also for further developments following similar fundamental principles.Item An energy efficient intelligent torque vectoring approach based on fuzzy logic controller and neural network tire forces estimator(2021-01-13) Parra, Alberto; Zubizarreta, Asier; Pérez, Joshué; Tecnalia Research & Innovation; CCAMIn electric vehicles (EVs) with multiple motors, torque vectoring (TV) control can effectively enhance the cornering response and safety. Moreover, TV systems can also improve the overall efficiency through an optimal torque distribution that also considers the power consumption. For such a complex control system with multiple objectives, intelligent control techniques have demonstrated to be one of the best alternatives. However, the works proposed in the literature do not handle both vehicle dynamics behavior and energy efficiency, and generally do not consider the real-time implementability of the developed controllers. To overcome the aforementioned isues, in this work, a novel torque vectoring approach is proposed, which uses a neural network-based vertical tire forces estimator and considers the regenerative braking capabilities of EVs. Moreover, the implementability of the controller in a heterogenous (FPGA and microcontroller) automotive suitable system on chip is addressed, ensuring its real-time capabilities. For the sake of validating the proposed approach, a set of experiments have been carried out in a hardware in the loop setup. The performance of the proposed TV approach has been compared with other two TV approaches from the literature, evaluating them in several challenging manoeuvres in high and low tire-road friction coefficient scenarios. Results show that the proposed approach not only is able to enhance the vehicle dynamics behavior but also to decrease the energy consumption about 13%.Item Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs(2016-07-01) Kretzschmar, Uli; Gomez-Cornejo, Julen; Astarloa, Armando; Bidarte, Unai; Del Ser, Javier; IAThe expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion.