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dc.contributor.authorKretzschmar, Uli
dc.contributor.authorGomez-Cornejo, Julen
dc.contributor.authorAstarloa, Armando
dc.contributor.authorBidarte, Unai
dc.contributor.authorDel Ser, Javier
dc.date.accessioned2016-03-08T16:04:40Z
dc.date.available2016-03-08T16:04:40Z
dc.date.issued2016-07
dc.identifier.citationReliability Engineering & System Safety, Vol. 151 (2016), pp. 1-9en
dc.identifier.issn0951-8320en
dc.identifier.urihttp://hdl.handle.net/11556/145
dc.description.abstractThe expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion.en
dc.description.sponsorshipMinisterio de Economia y Competitividad de España, TEC2014-53785-R Basque Government, IT394-10en
dc.language.isoengen
dc.publisherElsevieren
dc.titleSynchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designsen
dc.typearticleen
dc.identifier.doi10.1016/j.ress.2015.12.018en
dc.isiYesen
dc.rights.accessRightsembargoedAccessen
dc.subject.keywordsReliabilityen
dc.subject.keywordsTMRen
dc.subject.keywordsFPGAen
dc.subject.keywordsSynchronizationen
dc.subject.keywordsFault-recoveryen
dc.subject.keywordsProcessoren


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